What granularity does memory channel interleaving occur when enabled in BIOS?

Memory channel interleaving is a method of setting a physical address area which can be enabled in BIOS, so that all memory channels are alternately used to achieve best bandwidth and latency.

I want to know at what granularity memory channel interleaving occurs, in other words, what is the minimum memory block size that will be guided to the same memory channel when performing memory channel interleaving?

In this article, it could be 2^7 = 128 bytes.

In this whitepaper from fujitsu, "The channel interleave block size is based on a cache line size of 64 bytes"

Are there any official materials from Intel or AMD that can explain how this memory channel interleaving configuration works?

It's very reasonable to base interleaving on the cache line size multiplied by the number of memory channels.

Using a smaller interleaving granularity requires both (all) memory channels to be utilized when filling a cache line. Depending on the availability of the channels, that can severely increase latency.

Using coarser interleaving requires multiple access to a single channel for contiguous data.

Utilizing the memory channels in a round-robin fashion enables the best performance in terms of throughput and latency.

So, for the common cache line size of 64 bytes and two memory channels, the interleaving should be 128 bytes.